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nuvoton technology corp. 1 release date: may. 2013 http://www. nuvoton.com/ rev . a 5.1 n3290x data sheet arm9 26- based media processor
n3290 x datasheet nuvoton technology corp. 2 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 the information in this document is subject to change without notice. the nuvoton technology corp. shall not be liable for technical or editorial errors or omissi ons contained herein; nor for incidental or consequential damages resulting from the furnishing, performance, or use of this material. this documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electr onic medium or machine readable form without prior consent, in writing, from the nuvoton technology corp. nuvoton technology corp. all rights reserved.
n3290 x datasheet nuvoton technology corp. 3 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 n3290x arm9 26- based media processor table of contents 1. general description ................................................................................................................................... 5 1.1 applications .............................................................................................................................................. 5 2. features ........................................................................................................................................................... 6 3. pin diagram .................................................................................................................................................... 12 3.1 n32901u1dn (lqfp - 128) ..................................................................................................................... 12 3.2 n32901u2dn (lqfp - 128) ..................................................................................................................... 13 3.3 n32903u1dn (lqfp - 128) ..................................................................................................................... 14 3.4 n32905u1dn (lqfp - 128) ..................................................................................................................... 15 3.5 n32905u2dn (lqfp - 128) ..................................................................................................................... 16 3.6 N32903R1DN (tqfp - 64) ....................................................................................................................... 17 3.7 n32901r1dn (lqfp - 64) ....................................................................................................................... 18 4. pin description ............................................................................................................................................ 19 4.1 pin description & cross reference ........................................................................................................ 19 4.2 pin type description .............................................................................................................................. 28 5. e lectrical specificat ion ......................................................................................................................... 29 5.1 absolute maximum rating ..................................................................................................................... 29 5.2 dc characteristics (normal i/o) ............................................................................................................ 29 5.3 audio dac characteristics ..................................................................................................................... 30 5.4 adc characteristic s .................................................................................................................................. 31 5.5 ac characteristic s ( digital int erface ) ......................................................................................................... 31 5.6 power - on sequence ............................................................................................................................... 40 5.7 thermal characteristics of lqfp - 128 package ..................................................................................... 40 6. o r dering information .............................................................................................................................. 41 6.1 part number definition ........................................................................................................................... 41 6.2 difference between n32901u1dn, n32903u1dn, n 32905u1dn and n32905u2dn .......................... 41 7. package outline .......................................................................................................................................... 42
n3290 x datasheet nuvoton technology corp. 4 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 7.1 lqfp - 128 (14x14x1.4mm body, 0.4mm pitch) ..................................................................................... 42 7.2 tqfp - 64 (10x10x1.0mm body, 0. 5 mm pitch) ....................................................................................... 43 7.3 lqfp - 64 (10x10x1.4mm body, 0. 5 mm pitch) ....................................................................................... 46 8. revision history .......................................................................................................................................... 47
n3290 x datasheet nuvoton technology corp. 5 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 1. general description t he n3290x ux dn is built on the arm926ej - s cpu core and integrated with jpeg codec, cmos sensor interface , 32- channel spu (sound processin g unit), adc, dac, for meeting various k inds of application needs while saving the bom cost. the com bination of arm926 @ 2 0 0mhz, s ynchronous d ram , 2d bitblt accelerator, cmos image sensor interface, lcd panel interface, usb 1.1 host & usb2.0 hs device makes the n3290 x ux dn the best choice for lc d ela devices. maximum resolution for the n3290 x ux dn is xvga ( 1,024x768 ) @ tft lcd panel . t he 2d bitblt accelerator accelerates the graphic compution to make the rendering smooth and off - load cpu to save power consumption. the n3290 xux dn is well - positione d in terms of cost / performance for the applications wh ich bitmap graphics is extensively used or cmos image sensor (cis) interface is required . the n3290xux dn is for application under linux os and leverage the driver availability of emerging functionalitie s like wi - fi, browser, etc. on the other hand, the open source code environment also give the product development more flexible. to meet the different requirement of the overall system bom cost, the different size of dram is stacked with n3290x main soc in to one package, that is, multi - chip package (mcp). t he n3290 1u1 dn is particularly designed with the 128- pin lqfp package and the 1mbitx16 sdram is stacked inside the mcp . t he n3290 3u1 dn is particularly designed with the 128- pin lqfp package and the 4mbit x16 sdram is stacked inside the mcp . the 16mbitx16 sdram is stacked inside the n32905ux dn mcp to ensure higher performance and minimize the system design efforts, like emi & noise coupling. total bom cost could be reduced by employing 2 - layer pcb along wit h the elimination of damping resistors, emi prevention components, etc. advantages including, but not limited to, less pcb space, shorter lead time, and higher / reliable production yield. 1.1 applications ? ela (education al learning aid) ? hmi ? security ? home appliance ? advertisement
n3290 x datasheet nuvoton technology corp. 6 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 2. features ? cpu ? arm926ej - s 32 - bit risc cpu with 8kb i - cache & 8kb d - cache ? frequency up to 200mhz@1.8v core power operation voltage ? jtag interface supported for development and debug ging ? internal sr am & rom ? 8kb internal sram and 1 6 kb ibr internal booting rom supported ? ibr booting messages displayed by uart console for debug ging supported ? different system booting modes supported: ? memory card ? sd card ? sd - to - nand flash bridge ? raw nand flash ? spi flash ? usb ? edma (enhanced dma) ? totally 5 dma channels supported ? 4 peripheral dma channels for transfer between memory and on - chip peripherals, such as adc, uart and spi ? one dedicated channel for memory - to - memory transfer ? byte, half - word and word data width types su pported ? single and burst transfer modes supported ? block transfer supported in memory - to - memory transfer channel ? color format transformation supported in memory - to - memory transfer channel ? source color format could be rgb555, rgb565 and ycbcr422 ? destination color format could be rgb555, rgb565 and ycbcr422 ? auto reload supported for continuous data transfer ? interrupt generation supported in the half - of - transfer or end - of - transfer ? capture (cmos sensor i/f) ? ccir601 & ccir656 interfaces supported for connection to cmos image sensor ? r esolution up to 2 m pixel for still image capture, 640x480 (vga) resolution for mjpeg video streaming ? yuv422 and rgb565 color format supported for data - in from cmos sensor ? yuv422, rgb565, rgb555 and y - only color format supported for d ata storing to system memory ? planar and packet data format s supported for data storing to system memory ? image cropping supported with the cropping window up to 4096x2048 ? image scaling - down supported ? vertical and horizontal scaling - down for preview mode sup ported ? the scaling factor is n/m ? two pairs of configurable 8 - bit n and 8 - bit m for vertical and horizontal scaling - down ? the value of n has to equal to or less than m ? frame rate control supported ? combines two interlace fields to a single frame supported for data in from tv - decoder ? jpeg codec ? baseline sequential mode jpeg codec function compliant with iso/iec 10918 - 1
n3290 x datasheet nuvoton technology corp. 7 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 international jpeg standard supported. ? planar format ? support to encode interleaved ycbcr 4:2:2/4:2:0 and gray - level (y only) format image ? suppo rt to decode interleaved ycbcr 4:4:4/4:2:2/4:2:0/4:1:1 and gray - level (y only) format image ? support to decode ycbcr 4:2:2 transpose format ? support arbitrary width and height image encode and decode ? support three programmable quantization - tables ? support sta ndard default huffman - table and programmable huffman - table for decode ? support arbitrarily 1x~8x image up - scaling function for encode mode ? support down - scaling function for encode and decode modes ? support specified window decode mode ? support quantization - ta ble adjustment for bit - rate and quality control in encode mode ? support rotate function in encode mode ? packet format ? support to encode interleaved yuyv format input image, output bitstream 4:2:2 and 4:2:0 format ? support to decode interleaved ycbcr 4:4:4/4:2 :2/4:2:0 format image ? support decoded output image rgb555 , rgb565 and rgb888 format s . ? the encoded jpeg bit - stream format is fully compatible with jfif and exif standards ? support arbitrary width and height image encode and decode ? support three programmable quantization - tables ? support standard default huffman - table and programmable huffman - table for decode ? support arbitrarily 1x~8x image up - scaling function for encode mode ? support down - scaling function 1x~ 16x for y422 and y420, 1x~ 8x for y444 for decode mod e ? support specified window decode mode ? support quantization - table adjustment for bit - rate and quality control in encode mode ? 2d accelerator ? bit b lt operation ? 2x2 t ransform matrix with effects: ? scale ? translate ? rotate ? shear ? alpha blending and color transform ation supported ? source format for operations: supported color format of source bitmap ? fill ? rectangle fill with single color ? argb8888 ? fill with blending effect supported ? supported color format s ? source ? 16 bits/pixel ? rgb565 ? 32 bits/pixel ? argb8888 ? 1 bit/ pixel, 2 bits/pixel, 4 bits/pixel, 8 bits/pixel with rgb color palett e ? destination ? 16 bits/pixel ? rgb565 ? 32 bits/pixel ? argb8888
n3290 x datasheet nuvoton technology corp. 8 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 ? vpost ? 8/16/18/24 - bit sync type and 8/9/16/18/24 - bit mpu type tft lcd supported ? color format supported: ? ycbcr422, rgb565, rgb 555, and rgb888 color formats supported for data in ? ycbcr422, rgb565, rgb555, and rgb888 color formats supported for data out ? xga ( 1024x768 ) , svga (800x600), wvga (800x480), d1 (720x480), vga (640x480), wqvga (480x272), qvga (320x240) and hvga (640x240) re solution supported ? the maximum resolution is up to d1 (720x480) for tv output ? the maximum resolution is up to 1024x 768 for tft lcd panel for still image displaying ? the maximum resolution is up to 480x272 for tft lcd panel for mjpeg video displaying up to 2 5 fps. ? display scaler ? to fit different size of lcd panels ? horizontal: at most 4.0x scale ? vertical: at most 3.0x scale ? for sync type lcd: ? for 8 - bit bus ? ccir601 ycbcr422 packet mode (ntsc/pal) supported ? ccir601 rgb dummy mode (ntsc/pal) supported ? ccir656 in terface supported ? rgb through mode supported ? for 16/18/24 - bit bus ? parallel pixel data output mode (1 - pixel/1 - clock) ? ntsc/pal interlace & non - interlace output supported ? color format transform supported: ? color format transform between ycbcr422 and rgb565 ? col or format transform from ycbcr422 to rgb888 ? tv encoder supported ? dual screen, outputs to tv and lcd simultaneously with same content, supported ? lcd panel should be 320x240 mpu - type, or 8 - bit sync - type lcd panel with tv timing ? notch filter for ntsc supporte d to remove the rainbow color effect ? support osd function to overlap system information like battery life, brightness tuning, volume tuning or muting, etc. ? frame switch controller ? frame relation controlled between vpost and capture supported ? 2 modes suppo rted to switch frame buffer base ? frame ratio mode (16 selectable ratio) ? frame sync mode ? double/triple buffers supported ? spu (sound processing unit) ? 32 stereo channels supported ? pcm8/pcm16/ 4 - bit mdpcm/tone source format supported ? 7 - bit volume control suppo rted for each of 32 channels ? 5 - bit pan control supported for each l/r of 32 channels ? 10 - band equalizer supported ? special code supported for loop playing and event detection
n3290 x datasheet nuvoton technology corp. 9 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 ? audio dac ? 16 - bit stereo dac supported with headphone driver output ? h/w volume cont rol supported ? i 2 s controller ? i 2 s interface supported to connect external audio codec ? 16/18/20/24 - bit data format supported ? storage interface controller ? interface to nand flash: ? 8 - bit data bus width supported ? slc and mlc type nand flash supported ? 512b, 2kb , 4kb , and 8kb page size nand flash supported ? ecc4 , ecc8 , ecc12 and ecc15 algorithm supported for ecc generation, error detection and error correction ? pba - nand flash supported ? interface to sd/mmc/sdio/sdhc/micro - sd cards supported ? sd - to - nand flash bridge s upported ? dma function supported to accelerate the data transfer between system memory and nand flash or sd/mmc/sdio/sdhc/micro - sd ? usb device controller ? usb2.0 hs ( high - speed) x 1 port ? 6 configurable endpoints supported ? control, bulk, interrupt and isochro nous transfers supported ? suspend and remote wakeup supported ? usb host controller ? usb1.1 host one h/w engine, two pin locations. ? fully compliant with usb revision 1.1 specification ? open host controller interface (ohci) revision 1.0 compatible ? full - speed (1 2mbps) and low - speed (1.5mbps) usb devices supported ? control, bulk, interrupt and isochronous transfers supported ? timer & watch - dog timer ? two 32 - bit with 8 - bit pre - scalar timers supported ? one programmable 24 - bit watch - dog timer supported ? pwm ? 4 pwm channe l outputs supported ? 16 - bit counter supported for each pwm channel ? two 8 - bit pre - scalars supported and each pre - scalar shared by two pwm channels ? two clock - dividers supported and each divider shared by two pwm channels ? two dead - zone generators supported and each generator shared by two pwm channels ? auto reloaded mode and one - shot pulse mode supported ? capture function supported ? uart ? a high speed uart supported: ? baud rate is up to 1m bps ? 4 signals tx, rx, cts and rts supported
n3290 x datasheet nuvoton technology corp. 10 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 ? a normal uart supported: ? baud ra te is up to 115.2k bps ? 2 signals tx and rx supported only ? spi ? one spi controller is supported ? both master and slave mode are supported in spi interface ? two chip selection signals for two spi devices ? i2c ? one i2c channel supported ? compatible with philips?s i 2 c standard and only master mode supported ? multi - master operation supported ? advanced interrupt controller ? total 32 interrupt source supported ? configurable interrupt type: ? low - active level triggered interrupt ? high - active level triggered interrupt ? low - act ive edge (falling edge) triggered interrupt ? high - active edge (rising edge) triggered interrupt ? individual interrupt mask bit for each interrupt source ? 8 different priority levels supported ? daisy - chain priority mechanism supported for interrupts with same p riority level ? low priority interrupt automatic masking supported for interrupt nesting ? rtc ? independent power plane supported ? 32.768 khz crystal oscillation circuit supported ? time counter (second, minute, hour) and calendar counter (day, month, year) suppo rted ? alarm supported (second, minute, hour, day, month and year) ? 12/24 - hour mode and leap year supported ? alarm to wake chip up from standby mode or from power - down mode supported ? wake chip up from power - down mode by input pin supported ? power - off chip by re gister setting supported ? power - on timeout is supported for low battery protection ? gpio ? 80 programmable general purpose i/os supported and separated into 5 groups ? individual configuration supported for each i/o signal ? configurable interrupt control functio ns supported ? configurable de - bounce circuit supported for interrupt function ? adc ? multi - channel, 10 - bit adc supported ? 2 channels dedicated for 4 - wire resistive touch sensor inputs ? 2 channels dedicated for audio adc with microphone pre - amp & agc ? 3 channel s reserved f or various purposes , like lvd (low voltage detection) , keypad input , and light sensor ? input voltage range from 0 v ~ 3.3 v supported
n3290 x datasheet nuvoton technology corp. 11 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 ? maximum 25mhz input clock supported ? maximum 400k/s conversion rate supported ? lvr (low voltage reset) supported ? pow er management ? advanced power management including power down, deep standby, cpu standby , and normal operating modes ? normal operating mode ? core power is 1.8v and chip is in normal operation ? cpu standby mode ? core power is 1.8v and only arm cpu clock is turne d off ? deep standby mode ? core power is 1.8v and all ip clocks are turned off ? power down mode ? only the rtc power is on. other 3.3v and 1.8v power are off ? software support ? development tools ? bootloader / diagnostic program / nand writer program: ads 1.2 or rv ds 2.x or 3.x ? linux kernel (2.6.17.14) / system manager : gcc 4.2 ? turbowriter / sync tool: microsoft vc 6.0 ? nand flash file system ? fat12, fat16 and fat32 with long filename are supported ? hidden disk is supported ? ram disk is supported ? s/w audio library ? decod ers with adpcm / mp3 / acc / ogg / w ma format support ? 32 - polyphony wavetable midi synthesizer ? programmable sampling rate and target bit rate ? usb driver ? ms ( mass s torage ) c lass ? hid (human interface device) class ? operating voltage ? i/o: 3. 3v ? core : 1.8v for 2 00 mhz ? package ? lqfp - 128 (mcp, stacked with ddr @ 1.8v an d sdr @ 1.8 v )
n3290 x datasheet nuvoton technology corp. 12 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 3. pin diagram 3.1 n3290 1 u1 dn (lqfp -128) adac_hpout_l _ adac_hpvdd33 adac_hpvss33 mvddq mvssq mvddq mvssq mvref mvss vdd18 ud_cdet trst_ rst_ vdd33 rtc_vdd rtc_rpwr rtc_rwake_ rtc_xin rtc_xout adc_ain[3] / hur_rts / spi0_cs1_ / gpd[4] tdo / hur_cts / pwm3 / tdi / hur_rxd / pwm2 / tms / hur_txd / pwm1 / tck / spi1_cs1_ / pwm0 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / spclk sclko isda isck spi0_do spi0_di spi0_clk sddat[0] sddat[1] sddat[2] sddat[3] sdclk sdcmd xin xout mvssq mvddq mvssq mvddq mvdd vdd18 ud_vdd18 ud_vss ud_dm ud_dp ud_vdd33 ud_rext vss lvdata[17] / sd_cd_ / lmvsync / uhl_dp1 / / spi0_cs1_ / uhl_dm1 / sddat1[0] / gpb[1] / uhl_dp1 / sddat1[1] / gpb[0] / lmvsync / gpb[14] / wdt_rst_ / gpb[13] / / gpd[12] / / gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpe[1] svsync / / / / / / / / / / / / / / / / / / / / / / / n32901u1dn lqfp-128 1 10 20 30 4 0 5 0 6 0 70 80 90 1 0 0 1 1 0 1 2 0 1 2 8 / / mvref mvdd mvss shsync i2s_mclk sdclk1 gpb[2] gpb[3] gpb[4] gpb[5] gpb[6] gpa[11] gpa[10] gpe[8] gpe[9] sdcmd1 sddat1[3] sddat1[2] i2s_bclk i2s_ws i2s_dout i2s_din lmvsync spi1_cs1_ sddat2[1] sddat2[ 0] gpe[10] gpe[11] gpd[7 ] gpd[8] gpd[5] gpd[6] sddat2[3 ] sddat2[ 2] sdcmd2 sdclk2 spdata[0] spdata[1] svsync sfield urrxd urtxd vdd33 ncs0_ vss ncs1_ nale nre_ ncle nwr_ nbusy0_ nbusy1_ nd[7] nd[6] nd[5] nd[4 ] nd[3 ] nd[2] nd[1 ] nd[0] gpa[7] vdd18 vdd33 adac_vdd33 adac_vref adac_avss33 adac_hpout _r gpd[3] gpd[2] gpd[1] gpd[0] gpa[0] gpa[1] gpa[2] gpa[3] uhl_dm1 gpa[4] gpa[5] gpa[6] spi1_cs1_ shsync gpe[0] gpc[15] gpc[14] gpc[13] gpc[12] gpc[11] gpc[10] gpc[9] gpc[8] spdata[7] spdata[6] spdata[5] spdata[4] spdata[3] spdata[2] spdata[1] spdata[0] gpc[7] gpc[6] gpc[5] gpc[4 ] gpc[3] gpc[2] gpc [1] gpc[0] gpd[11] wdt_rst _ gpd[10] gpd[9] gpb[15] lvdata[0 ] lvdata[1 ] lvdata[2] lvdata[3 ] lvdata[4] lvdata[5] lvdata[6] lvdata[7] lvdata[8] lvdata[9] lvdata[10] lvdata[11] lvdata[12] lvdata[13] lvdata[14] lvdata[15] lvdata[16] lvde lvsync lhsync vdd18 lpclk vdd33 adc_vss33 adc_ain [2] mic_in_p mic_in_m adc_ain[1] adc_ain [0] adc_vdd33 adc_tp _yp adc_tp_ xp adc_tp_ xm adc_tp _ym / / / / / / / / / / spi0_cs0_ / gpd[14] gpd[13] gpd[15]
n3290 x datasheet nuvoton technology corp. 13 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 3.2 n3290 1u2 dn (lqfp -128) adac_hpout_ l _ adac_hpvdd33 adac_hpvss33 mvddq (3.3v) mvssq mvddq (3.3v) mvssq nc mvss vdd18 ud_cdet trst_ rst_ vdd33 rtc_vdd rtc_rpwr rtc_rwake_ rtc_xin rtc_xout adc_ain[3] / hur_rts / spi0_cs 1_ / gpd[4] tdo / hur_cts / pwm3 / tdi / hur_rxd / pwm2 / tms / hur_txd / pwm1 / tck / spi1_cs1_ / pwm0 / / / / / / / / / / / / / / / / / / / spclk sclko isda isck spi0_do spi0_di spi0_clk sddat[0] sddat[1] sddat[2] sddat[3] sdclk sdcmd xin xout mvssq mvddq(3. 3v) mvssq mvddq(3.3v) mvdd(3.3v) vdd18 ud_vdd18 ud_vss ud_dm ud_dp ud_vdd33 ud_rext vss lvdata[17] / sd_cd_ / lmvsync / uhl_dp1 / / spi0_cs1_ / uhl_dm1 / sddat1[0 ] / gpb[1] / uhl_dp1 / sddat1[1 ] / gpb[0] / lmvsync / gpb[14] / wdt_rst_ / gpb[13] / / gpd[12] / / gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpe[1] svsync / / / / / / / / / / / / / / / / / / / / / / / n32901u2dn lqfp-128 1 10 20 30 4 0 5 0 6 0 70 80 90 1 0 0 1 1 0 1 2 0 1 2 8 / / nc mvdd mvss gpa[11] gpa[10] gpe[8] gpe[9] lmvsync spi1_cs1_ sddat2[1] sddat2[0] gpe[10] gpe[11] gpd[7] gpd[8] gpd[5] gpd[6] sddat2[3] sddat2[2] sdcmd2 sdclk2 urrxd urtxd vdd33 ncs0_ vss ncs1_ nale nre_ ncle nwr_ nbusy0_ nbusy1_ nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] gpa[7] vdd18 tvdac_vss33 adac_vdd33 adac_vref adac_avss33 adac_hpout_r gpd[3] gpd[2] gpd[1] gpd[0] gpa[0] gpa[1] gpa[2] gpa[3] uhl_dm1 gpa[4] gpa[5] gpa[6] spi1_cs1_ shsync gpe[0] gpc[15] gpc[14] gpc[13] gpc[12] gpc[11] gpc[10] gpc[9] gpc[8] spdata[7] spdata[6] spdata[5] spdata[4] spdata[3] spdata[2] spdata[1] spdata[0] gpc[7] gpc[6] gpc[5] gpc[4] gpc[3] gpc[2] gpc[1] gpc[0] gpd[11] wdt_rst_ gpd[10] gpd[9] gpb[15] lvdata[0] lvdata[1] lvdata[2] lvdata[3] lvdata[4] lvdata[5] lvdata[6] lvdata[7] lvdata[8] lvdata[9] lvdata [10] lvdata[11] lvdata[12] lvdata[13] lvdata[14] lvdata[15] lvdata[16] lvde lvsync lhsync vdd18 lpclk vdd33 adc_vss33 adc_ain[2] mic_in_ p mic_in_m adc_ain[ 1] adc_ain[0 ] adc_vdd33 adc_tp_yp adc_tp_xp adc_tp_ xm adc_tp_ym / / / / / / / / / / spi0_cs 0_ / gpd[14] gpd[13] gpd[15] tvdac_tvout tvdac_comp tvdac_vdd33 tvdac_vref tvdac_rext
n3290 x datasheet nuvoton technology corp. 14 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 3.3 n3290 3u1 dn (lqfp -128) adac_hpout_l _ adac_hpvdd33 adac_hpvss33 mvddq mvssq mvddq mvssq mvref mvss vdd18 ud_cdet trst_ rst_ vdd33 rtc_vdd rtc_rpwr rtc_rwake_ rtc_xin rtc_xout adc_ain[3] / hur_rts / spi0_cs1_ / gpd[4] tdo / hur_cts / pwm3 / tdi / hur_rxd / pwm2 / tms / hur_txd / pwm1 / tck / spi1_cs1_ / pwm0 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / spclk sclko isda isck spi0_do spi0_di spi0_clk sddat[0] sddat[1] sddat[2] sddat[3] sdclk sdcmd xin xout mvssq mvddq mvssq mvddq mvdd vdd18 ud_vdd18 ud_vss ud_dm ud_dp ud_vdd33 ud_rext vss lvdata[17] / sd_cd_ / lmvsync / uhl_dp1 / / spi0_cs1_ / uhl_dm1 / sddat1[0] / gpb[1] / uhl_dp1 / sddat1[1] / gpb[0] / lmvsync / gpb[14] / wdt_rst_ / gpb[13] / / gpd[12] / / gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpe[1] svsync / / / / / / / / / / / / / / / / / / / / / / / n32903u1dn lqfp-128 1 10 20 30 4 0 5 0 6 0 70 80 90 1 0 0 1 1 0 1 2 0 1 2 8 / / mvref mvdd mvss shsync i2s_mclk sdclk1 gpb[2] gpb[3] gpb[4] gpb[5] gpb[6] gpa[11] gpa[10] gpe[8] gpe[9] sdcmd1 sddat1[3] sddat1[2] i2s_bclk i2s_ws i2s_dout i2s_din lmvsync spi1_cs1_ sddat2[1] sddat2[0] gpe[10] gpe[11] gpd[7] gpd[8] gpd[5] gpd[6] sddat2[3] sddat2[2] sdcmd2 sdclk2 spdata[0] spdata[1] svsync sfield urrxd urtxd vdd33 ncs0_ vss ncs1_ nale nre_ ncle nwr_ nbusy0_ nbusy1_ nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] gpa[7] vdd18 vdd33 adac_vdd33 adac_vref adac_avss33 adac_hpout_ r gpd[3] gpd[2] gpd[1] gpd[0] gpa[0] gpa[1] gpa[2] gpa[3] uhl_dm1 gpa[4] gpa[5] gpa[6] spi1_cs1_ shsync gpe[0] gpc[15] gpc[14] gpc[13] gpc[12] gpc[11] gpc[10] gpc[9] gpc[8] spdata[7] spdata[6] spdata[5] spdata[4] spdata[3] spdata[2] spdata[1] spdata[0] gpc[7] gpc[6] gpc[5] gpc[4] gpc[3] gpc[2] gpc [1] gpc[0] gpd[11] wdt_rst_ gpd[10] gpd[9] gpb[15] lvdata[0] lvdata[1] lvdata[2] lvdata[3] lvdata[4] lvdata[5] lvdata[6] lvdata[7] lvdata[8] lvdata[9] lvdata[10] lvdata[11] lvdata[12] lvdata[13] lvdata[14] lvdata[15] lvdata[16] lvde lvsync lhsync vdd18 lpclk vdd33 adc_vss33 adc_ain[ 2] mic_in_p mic_in_m adc_ain[1] adc_ain[0] adc_vdd33 adc_tp_yp adc_tp_ xp adc_tp_xm adc_tp_ym / / / / / / / / / / spi0_cs0_ / gpd[14] gpd[13] gpd[15]
n3290 x datasheet nuvoton technology corp. 15 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 3.4 n32905u1 d n ( lqfp -128) adac_hpout_l _ adac_hpvdd33 adac_hpvss33 mvddq mvssq mvddq mvssq mvref mvss vdd18 ud_cdet trst_ rst_ vdd33 rtc_vdd rtc_rpwr rtc_rwake_ rtc_xin rtc_xout adc_ain[3] / hur_rts / spi0_cs1_ / gpd[4] tdo / hur_cts / pwm3 / tdi / hur_rxd / pwm2 / tms / hur_txd / pwm1 / tck / spi1_cs1_ / pwm0 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / spclk sclko isda isck spi0_do spi0_di spi0_clk sddat[0] sddat[1] sddat[2] sddat[3] sdclk sdcmd xin xout mvssq mvddq mvssq mvddq mvdd vdd18 ud_vdd18 ud_vss ud_dm ud_dp ud_vdd33 ud_rext vss lvdata[17] / sd_cd_ / lmvsync / uhl_dp1 / / spi0_cs1_ / uhl_dm1 / sddat1[0] / gpb[1] / uhl_dp1 / sddat1[1] / gpb[0] / lmvsync / gpb[14] / wdt_rst_ / gpb[13] / / gpd[12] / / gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpe[1] svsync / / / / / / / / / / / / / / / / / / / / / / / n32905u1dn lqfp-128 1 10 20 30 4 0 5 0 6 0 70 80 90 1 0 0 1 1 0 1 2 0 1 2 8 / / mvref mvdd mvss shsync i2s_mclk sdclk1 gpb[2] gpb[3] gpb[4] gpb[5] gpb[6] gpa[11] gpa[10] gpe[8] gpe[9] sdcmd1 sddat1[3] sddat1[2] i2s_bclk i2s_ws i2s_dout i2s_din lmvsync spi1_cs1_ sddat2[1] sddat2[0] gpe[10] gpe[11] gpd[7] gpd[8] gpd[5] gpd[6] sddat2[3] sddat2[2] sdcmd2 sdclk2 spdata[0] spdata[1] svsync sfield urrxd urtxd vdd33 ncs0_ vss ncs1_ nale nre_ ncle nwr_ nbusy0_ nbusy1_ nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] gpa[7] vdd18 vdd33 adac_vdd33 adac_vref adac_avss33 adac_hpout_r gpd[3] gpd[2] gpd[1] gpd[0] gpa[0] gpa[1] gpa[2] gpa[3] uhl_dm1 gpa[4] gpa[5] gpa[6] spi1_cs1_ shsync gpe[0] gpc[15] gpc[14] gpc[13] gpc[12] gpc[11] gpc[10] gpc[9] gpc[8] spdata[7] spdata[6] spdata[5] spdata[4] spdata[3] spdata[2] spdata[1] spdata[0] gpc[7] gpc[6] gpc[5] gpc[4] gpc[3] gpc[2] gpc [1] gpc[0] gpd[11] wdt_rst_ gpd[10] gpd[9] gpb[15] lvdata[0] lvdata[1] lvdata[2] lvdata[3] lvdata[4] lvdata[5] lvdata[6] lvdata[7] lvdata[8] lvdata[9] lvdata[10] lvdata[11] lvdata[12] lvdata[13] lvdata[14] lvdata[15] lvdata[16] lvde lvsync lhsync vdd18 lpclk vdd33 adc_vss33 adc_ain[2] mic_in_p mic_in_m adc_ain[1] adc_ain[0] adc_vdd33 adc_tp_yp adc_tp_ xp adc_tp_xm adc_tp_ym / / / / / / / / / / spi0_cs0_ / gpd[14] gpd[13] gpd[15]
n3290 x datasheet nuvoton technology corp. 16 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 3.5 n3290 5u2 dn ( lqfp -128) adac_hpout_l _ adac_hpvdd33 adac_hpvss33 mvddq mvssq mvddq mvssq mvref mvss vdd18 ud_cdet trst_ rst_ vdd33 rtc_vdd rtc_rpwr rtc_rwake_ rtc_xin rtc_xout adc_ain[3] / hur_rts / spi0_cs1_ / gpd[4] tdo / hur_cts / pwm3 / tdi / hur_rxd / pwm2 / tms / hur_txd / pwm1 / tck / spi1_cs1_ / pwm0 / / / / / / / / / / / / / / / / / / / spclk sclko isda isck spi0_do spi0_di spi0_clk sddat[0] sddat[1] sddat[2] sddat[3] sdclk sdcmd xin xout mvssq mvddq mvssq mvddq mvdd vdd18 ud_vdd18 ud_vss ud_dm ud_dp ud_vdd33 ud_rext vss lvdata[17] / sd_cd_ / lmvsync / uhl_dp1 / / spi0_cs1_ / uhl_dm1 / sddat1[0] / gpb[1] / uhl_dp1 / sddat1[1] / gpb[0] / lmvsync / gpb[14] / wdt_rst_ / gpb[13] / / gpd[12] / / gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpe[1] svsync / / / / / / / / / / / / / / / / / / / / / / / n32905u2dn lqfp-128 1 10 20 30 4 0 5 0 6 0 70 80 90 1 0 0 1 1 0 1 2 0 1 2 8 / / mvref mvdd mvss gpa[11] gpa[10] gpe[8] gpe[9] lmvsync spi1_cs1_ sddat2[1] sddat2[0] gpe[10] gpe[11] gpd[7] gpd[8] gpd[5] gpd[6] sddat2[3] sddat2[2] sdcmd2 sdclk2 urrxd urtxd vdd33 ncs0_ vss ncs1_ nale nre_ ncle nwr_ nbusy0_ nbusy1_ nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] gpa[7] vdd18 tvdac_vss33 adac_vdd33 adac_vref adac_avss33 adac_hpout_r gpd[3] gpd[2] gpd[1] gpd[0] gpa[0] gpa[1] gpa[2] gpa[3] uhl_dm1 gpa[4] gpa[5] gpa[6] spi1_cs1_ shsync gpe[0] gpc[15] gpc[14] gpc[13] gpc[12] gpc[11] gpc[10] gpc[9] gpc[8] spdata[7] spdata[6] spdata[5] spdata[4] spdata[3] spdata[2] spdata[1] spdata[0] gpc[7] gpc[6] gpc[5] gpc[4] gpc[3] gpc[2] gpc[1] gpc[0] gpd[11] wdt_rst_ gpd[10] gpd[9] gpb[15] lvdata[0] lvdata[1] lvdata[2] lvdata[3] lvdata[4] lvdata[5] lvdata[6] lvdata[7] lvdata[8] lvdata[9] lvdata [10] lvdata[11] lvdata[12] lvdata[13] lvdata[14] lvdata[15] lvdata[16] lvde lvsync lhsync vdd18 lpclk vdd33 adc_vss33 adc_ain[2] mic_in_p mic_in_m adc_ain[1] adc_ain[0] adc_vdd33 adc_tp_yp adc_tp_ xp adc_tp_xm adc_tp_ym / / / / / / / / / / spi0_cs0_ / gpd[14] gpd[13] gpd[15] tvdac_tvout tvdac_comp tvdac_vdd33 tvdac_vref tvdac_rext
n3290 x datasheet nuvoton technology corp. 17 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 3.6 n3290 3r1 dn ( t qfp -64) N32903R1DN tqfp-64 (10 x 10 x 1.0mm) ( pitch 0.5mm) 50 55 vdd33 / gpb[6] i2s_din / 60 gpb[5] i2s_dout / / gpb[4] i2s_ws sfield / / gpb[3] i2s_bclk svsync spclk uhl_dm1 / / gpb[1] / mic_in_m adc_ain[1] / mic_in_p adc_ain[0] adc_vdd33 30 adc_vss vdd33 vdd18 gpc[8] spdata[0] / gpc[9] spdata[1] / 25 gpc[10] spdata[2] / gpc[11] spdata[3] / gpc[12] spdata[4] / gpc[13] spdata[5] / 20 gpc[14] spdata[6] / gpc[15] spdata[7] / adac_hpout_l adac_hpvdd33 adac_hpvss33 45 mvdd18 ud_cdet 40 rst_ 35 / uhl_dp1 gpa[3] / uhl_dm1 gpa[4] 1 / spi0_cs0_ gpd[13] spi0_di / gpd[14] spi0_do / gpd[15] xin xout 10 mvref pll_vdd18 ud_dm ud_dp ud_vdd33 15 ud_rext mvref vss / spi0_cs1_ gpa[5] adc_ain[2] / / gpa[11] gpa[10] urrxd urtxd sddat[0] sddat[1] sddat[2] sddat[3] sdclk sdcmd gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpa[7] vdd18 adac_avss33 adac_vref adac_vdd33 / / shsync i2s_mclk gpb[2] spclko uhl_dp1 / / gpb[0] spi0_clk gpd[12] / 5 / sd_cd gpa[1] hur_rxd / pwm2 / gpd[2] hur_txd / pwm1 / gpd[1] vdd18 adac_hpout_r
n3290 x datasheet nuvoton technology corp. 18 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 3.7 n3290 1 r1dn ( l qfp -64) n32901r1dn lqfp -64 (10 x 10 x 1.4mm) ( pitch 0.5mm) 50 55 vdd33 / gpb[6] i2s_din / 60 gpb[5] i2s_dout / / gpb[4] i2s_ws sfield / / gpb[3] i2s_bclk svsync spclk uhl_dm1 / / gpb[1] / mic_in_m adc_ain[1] / mic_in_p adc_ain[0] adc_vdd33 30 adc_vss vdd33 vdd18 gpc[8] spdata[0] / gpc[9] spdata[1] / 25 gpc[10] spdata[2] / gpc[11] spdata[3] / gpc[12] spdata[4] / gpc[13] spdata[5] / 20 gpc[14] spdata[6] / gpc[15] spdata[7] / adac_hpout_l adac_hpvdd33 adac_hpvss33 45 mvdd33 ud_cdet 40 rst_ 35 / uhl_dp1 gpa[3] / uhl_dm1 gpa[4] 1 / spi0_cs0_ gpd[13] spi0_di / gpd[14] spi0_do / gpd[15] xin xout 10 vss pll_vdd18 ud_dm ud_dp ud_vdd33 15 ud_rext vss vss / spi0_cs1_ gpa[5] adc_ain[2] / / gpa[11] gpa[10] urrxd urtxd sddat[0] sddat[1] sddat[2] sddat[3] sdclk sdcmd gpe[7] / gpe[4] / gpe[5] / gpe[6] / gpe[3] / gpe[2] / gpa[7] vdd18 adac_avss33 adac_vref adac_vdd33 / / shsync i2s_mclk gpb[2] spclko uhl_dp1 / / gpb[0] spi0_clk gpd[12] / 5 / sd_cd gpa[1] hur_rxd / pwm2 / gpd[2] hur_txd / pwm1 / gpd[1] vdd18 adac_hpout_r
n3290 x datasheet nuvoton technology corp. 19 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 4. pin description 4.1 pin description & cross reference p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn clock & reset xin i 27mhz/12mhz crystal input xout o 27mhz/12mhz crystal output rst_ i osu system reset, input, low act ive watch - dog reset, output, low active jtag interface tck iod jtag interface test clock, input spi1_cs1_ spi port 1 device select 1, output, low active pwm0 pwm channel 0 gpd[0] gpio port d bit 0 tms io u jtag interface test mode select, input hur_txd high - speed uart tx data, output pwm1 pwm channel 1 gpd[1] gpio port d bit 1 tdi io u jtag interface test data in, input hur_rxd high - speed uart rx data, input pwm2 pwm channel 2 gpd[2] gpio port d bit 2 tdo io u jtag interface test data out, output hur_cts high - speed uart clear - to - send, input, low active pwm3 pwm channel 3 gpd[3] gpio port d bi t 3 trst_ io u jtag interface test reset, input, low active hur_rts high - speed uart reset - to - send, output, low active spi0_cs1_ spi port 0 device select 1, output, low active gpd[4] gpio port d bit 4
n3290 x datasheet nuvoton technology corp. 20 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn nand inte rface ncs0_ io u nand interface chip select 0, output, low active sddat2[1] sd port 2 data bit 1 gpe[8] gpio port e bit 8 ncs1_ io u nand interface chip select 1, output, low active sddat2[0] sd port 2 data bit 0 gpe[9] gpio port e bit 9 nale io u nand interface address - latch - enable, output, high active gpe[10] gpio port e bit 10 ncle io u nand interface command - latch - enable, output, high active gpe[11] gpio port e bit 11 nbusy0_ io u nand interface busy 0, input, low active sddat2[3] sd port 2 data bit 3 gpd[5] gpio port d bit 5 nbusy1_ io u nand interface busy 1, input, low active sddat2[2] sd port 2 data bit 2 gpd[6] gpio port d bit 6 nre_ io u nand interface read enable, output, low active sdclk2 sd port 2 clock, output gpd[7] gpio port d bit 7 nwr_ io u nand interface write enable, output, low active sd cmd2 sd port 2 command/response gpd[8] gpio port d bit 8 nd[7:0] io u nand interface data bit [7:0] chipcfg[7:0] chip power - on configuration bit [7:0], input sensor/video - in interface
n3290 x datasheet nuvoton technology corp. 21 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn sclko io u clock to sensor module , output uhl_dp1 usb host like interface, dp sddat1[1] sd port 1 data bit 1 gpb[0] gpio port b bit 0 spclk io u sensor interface pixel clock, input uhl_dm1 usb host like interface, dm sddat1[ 0] sd port 1 data bit 0 gpb[1] gpio port b bit 1 svsync io u sensor interface vsync, input i2s_bclk i2s interface clock, input sdcmd1 sd port 1 command/response gpb[3] gpio port b bit 3 sfield io u se nsor interface even/odd field indicator, input i2s_ws i2s interface word select, output sddat1[3] sd port 1 data bit 3 gpb[4] gpio port b bit 4 spdata[0] io u sensor interface data bit 0, input i2s_dout i2s interface data output sddat1[2] sd port 1 data bit 2 gpb[5] gpio port b bit 5 spdata[1] io u sensor interface data bit 1, input i2s_din i2s interface data input gpb[6] gpio port b bit 6 i2c interf ace isck io u i2c interface clock, output gpb[13] gpio port b bit 13 isda io u i2c interface data lmvsync mpu mode vsync, output lfmark frame mark, input gpb[14] gpio port b bit 14
n3290 x datasheet nuvoton technology corp. 22 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn lcd/display in terface lpclk io u lcd interface pixel clock, output gpb[15] gpio port b bit 15 lhsync io u lcd interface hsync, output, high active gpd[9] gpio port d bit 9 lvsync io u lcd interface vsync, output, high active gpd[10] gpio port d bit 10 lvde io u lcd interface data enable, output, high active gpd[11] gpio port d bit 11 lvdata[0] io u lcd interface data bit 0 gpc[0] gpio port c bit 0 lvdata[1] io u lcd i nterface data bit 1 gpc[1] gpio port c bit 1 lvdata[2] io u lcd interface data bit 2 gpc[2] gpio port c bit 2 lvdata[3] io u lcd interface data bit 3 gpc[3] gpio port c bit 3 lvdata[4] io u lcd interface data bit 4 gpc[4] gpio port c bit 4 chipcfg[8] chip power - on configuration bit [8], input lvdata[5] io u lcd interface data bit 5 gpc[5] gpio port c bit 5 chipcfg[9] chip power - on configuratio n bit [9], input lvdata[6] io u lcd interface data bit 6 gpc[6] gpio port c bit 6 chipcfg[10] chip power - on configuration bit [10], input lvdata[7] io u lcd interface data bit 7 gpc[7] gpio port c bit 7 lvdata[8] io u lcd interface data bit 8
n3290 x datasheet nuvoton technology corp. 23 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn kpi_si[0] kpi scan in bit 0 spdata[0] sensor interface data bit 0, input gpc[8] gpio port c bit 8 lvdata[9] io u lcd interface data bit 9 kpi_si[1] kpi sc an in bit 1 spdata[1] sensor interface data bit 1, input gpc[9] gpio port c bit 9 lvdata[10] io u lcd interface data bit 10 kpi_si[2] kpi scan in bit 2 spdata[2] sensor interface data bit 2, input g pc[10] gpio port c bit 10 lvdata[11] io u lcd interface data bit 11 kpi_si[3] kpi scan in bit 3 spdata[3] sensor interface data bit 3, input gpc[11] gpio port c bit 11 lvdata[12] io u lcd interface data bit 12 kpi_si[4] kpi scan in bit 4 spdata[4] sensor interface data bit 4, input gpc[12] gpio port c bit 12 lvdata[13] io u lcd interface data bit 13 kpi_si[5] kpi scan in bit 5 spdata[5] sensor interface data bit 5, input gpc[13] gpio port c bit 13 lvdata[14] io u lcd interface data bit 14 kpi_si[6] kpi scan in bit 6 spdata[6] sensor interface data bit 6, input gpc[14] gpio port c bit 14 l vdata[15] io u lcd interface data bit 15 kpi_si[7] kpi scan in bit 7 spdata[7] sensor interface data bit 7, input
n3290 x datasheet nuvoton technology corp. 24 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn gpc[15] gpio port c bit 15 lvdata[1 6 ] io u lcd interface data bit 16 shsync sensor inter face hsync, input gpe[0] gpio port e bit 0 lvdata[1 7 ] io u lcd interface data bit 17 svsync sensor interface vsync, input gpe[1] gpio port e bit 1 uart interface urtxd io u uart tx data, output spi1_cs1_ spi port 1 device select 1, output, low active gpa[10] gpio port a bit 10 urrxd io u uart rx data, input lmvsync mpu mode vsync, output lfmark frame mark, input gpa[11] gpio port a bit 11 spi 0 interface spi0_clk io u spi port 0 clock output in master mode input in slave mode gpd[12] gpio port d bit 12 spi0_cs0_ io u spi port 0 device select 0, low active output in master mode input in slave mode gpd[13] gpio port d bit 13 spi0_di io u spi port 0 data input gpd[14] gpio port d bit 14 spi0_do io u spi port 0 data output gpd[15] gpio port d bit 15 sd card interface sdclk io u sd port 0 clock, output
n3290 x datasheet nuvoton technology corp. 25 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn gpe[7] gpio port e bit 7 sdcmd io u sd port 0 command/response gpe[6] gpio port e bit 6 sddat[0] io u sd port 0 data bit 0 gpe[2] gpio port e bit 2 sddat[1] io u sd port 0 data bit 1 gpe[3] gpio port e bit 3 sddat[2] io u sd port 0 data bit 2 gpe[4] gpio port e bit 4 sddat[3] io u sd port 0 data bit 3 gpe[5] gpio port e bit 5 gpio a gpa[0] io u gpio port a bit 0 gpa[1] io u gpio port a bit 1 sd_cd_ sd card detect, input, low active gpa[2] io u gpio port a bit 2 lmvsync mpu mode vsync, output lfmark frame mark, input kpi_so[0] kpi scan out bit 0 gpa[3] io u gpio port a bit 3 uhl_dp1 usb host 1.0 lite port 1, d+ kpi_so[1] kpi scan out bit 1 gpa[4] io u gpio port a bit 4 uhl_dm1 usb host 1.0 lite port 1, d - kpi_so[2] kpi scan out bit 2 gpa[5] io u gpio port a bit 5 spi0_cs1_ spi port 0 device select 1, output, low active kpi_so[3] kpi scan out bit 3 gpa[6] io u gpio port a bit 6 spi1_cs1_ spi port 1 device select 1, output, low
n3290 x datasheet nuvoton technology corp. 26 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn active kpi_so [4] kpi scan out bit 4 gpa[7] io u gpio port a bit 7 kpi_so[5] kpi scan out bit 5 rtc (real time clock) rtc_xin (32768hz) i 32768hz crystal input rtc_xout (32768hz) o 32768hz crystal output rtc_rwa ke_ i wakeup enable, input, low active rtc_rpwr o d power enable, open - drain usb 2.0 device interface ud_cdet i usb device connect detect, input, high active ud_dp io usb 2.0 device d+ ud_dm io usb 2. 0 device d - ud_rext io external resistor connect recommend to connect 12.1k ? resistor to ground for usb 2.0 phy tv out tvdac_tvout o composite/chroma o utput connect an external 75 ? resistor to ground of tvdac as tv terminal i mpedence tvdac_rext i o external r esistor c onnection recommend to connect 160 ? resistor to ground of tvdac tvdac_comp o external c apacitor c onnection c onnect 0.1uf capacitor to vdd33 of tvdac tvdac_vref o reference v oltage o utp ut c onnect 0.1uf capacitor to ground of tvdac adc & touch panel adc_ain[3] i adc analog input channel 3 adc_ain[2] i adc analog input channel 2
n3290 x datasheet nuvoton technology corp. 27 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn adc_ain[1] i adc analog input channel 1 mic_in_m i microph one negative input adc_ain[0] i adc analog input channel 0 mic_in_p i microphone positive input adc_tp_yp i touch panel yp adc_tp_xp i touch panel xp adc_tp_xm i touch panel xm adc_tp_ym i touch panel ym audio dac adac_hpout_r o audio headphone right channel output adac_hpout_l o audio headphone left channel output adac_ vref o audio dac reference voltage output recommend to connect 1uf capacitor to ground of audio dac power/ground mvref p reference voltage for sdram i/f useless if sdr sdram used . it should be mvdd/2 if ddr/ddr2/lpddr sdram used mvref_gnd_shi elding g ground shielding for reference voltage m vdd 18 p sdram i/f power (1.8v) mvdd33 p sdram i/f power (3.3v) mvss g sdram i/f ground (0v) mvddq p sdram i/f power (1.8v) mvssq g sdram i/f ground (0v) rtc_vdd p rtc core, i/f & 32768hz c rystal power ud_vdd33 p usb 2.0 phy power (3.3v) ud_vss33 g usb 2.0 phy ground (0v) ud_vdd18 p usb 2.0 phy power (1.8v) ud_vss18 g usb 2.0 phy ground (0v) tvdac_vdd33 p tv dac power ( 3.3v)
n3290 x datasheet nuvoton technology corp. 28 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 p in name i/o type description n32901u1dn n32901u2dn n3290 3u1 dn n3290 5u1 dn n3290 5u2 dn N32903R1DN n32901r1dn tvdac_vss33 g tv dac ground (0v) adc_vdd33 p adc power (3.3v) adc_vss33 g adc ground (0v) adac_hpvdd33 p audio dac headphone driver power (3.3v) adac_hpvss33 g au dio dac headphone drive r ground (0v) adac_avdd33 p audio dac power (3.3v) adac_avss33 g au dio dac ground (0v) vdd33 p i/o power (3.3v) vdd18 p core logic power (1.8v) vss g ground (0v) 4.2 pin type description type description i input o output od open drain o utput io input / output iod input with pull - d own / output iou input with pull - up / output iosu input with schmitt trigger & pull - up / output p power g ground
n3290 x datasheet nuvoton technology corp. 29 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5. electrical specifica tion 5.1 absolute maximum rating parameters values ambient t emperature - 2 0 c ~ 85 c storage t emperature - 40 c ~ 125 c voltage on any pin - 0.3v ~ 3.6v power s upply v oltage ( c ore l ogic) - 0.5v ~ 2.5v power s upply v oltage ( i/o buffer ) - 0.5v ~ 4.6v inject ion c urrent ( l atch - u p t esting) 100ma crystal frequency 2mhz ~ 27mhz 5.2 dc characteristics (normal i/o) symbol parameter condition min. typ. max. unit vdd33 i/o buffer post - driver voltage 3.0 3.3 3.6 v mvdd33 sdram operation voltage 3.0 3.3 3.6 v vdd18 core logic and i/o buffer pre - driver voltage 200mhz 1.62 1.8 1.98 v mvdd18 ddr operation voltage 100mhz 1.7 1.8 1.9 v mvddq / mvdd ddr operation voltage 100mhz 1.7 1.8 1.9 v rtc_vdd rtc power supply 1.2 - 1.8 v i rtc_vdd rtc supply current rtc_vdd n3290 x datasheet nuvoton technology corp. 30 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 symbol parameter condition min. typ. max. unit i oz tri - state output leakage current - 10 - 10 ua r pu pull - up resistor 39 65 116 k ? r pd pull - down resistor 40 56 108 k ? v o l output low voltage - - 0.4 v v oh output high voltage 2.4 - - v i ol low level output current 4ma i/o v ol = 0.4v - 4.0 - ma i oh high level output current 4ma i/o v oh = 2.4v - 5.9 - ma 5.3 audio dac characteristic s test conditions: rl = 10k / 50pf , bw = 2 0 hz ~ 2 0 khz , f req.= 1khz , sample rate = 48k hz. parameter min typ max unit operating voltage 3.0 3.3 3.6 v reference voltage - dac_vdd/2 - v reference capacitor - 0.1 - uf full scale output voltage - 1.32 - vrms maximum output power - - 52 mw maximum output power @ 32ohm load - - 46 mw maximum output power @ 16ohm load - - 41 mw l - channel snr - 86 - dbv r - channel snr - 85 - dbv l - channel thd+n - - 64 - db r - channel thd+n - - 64 - db l - channel thd+n @ 32ohm load - - 63 - db r - channel thd+n @ 32ohm load - - 63 - db l - channel thd+n @ 16ohm load - - 62 - db r - channel thd+n @ 16ohm load - - 62 - db
n3290 x datasheet nuvoton technology corp. 31 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.4 a d c characteristic s parameter min . typ . max . unit sar adc input voltage range 3.0 - 3.6 v resolution of adc - - 10 bit signal - to - noise plus distortion of adc from line in - tbd - db integral non - linearity of adc - 2.0 - lsb differential non - linearity of adc - 0. 8 - lsb no missing code - 10 - bit ad conversion rate=adcclk/16 - - 400 k hz 5.5 ac characteristic s ( digital interface ) 5.5.1 clock input cha racteristics xin t xin t xinwl t xinwh f xin = 1 / t xin xin duty = t xinwh / ( t xinwh + t xinwl ) symbol parameter min. typ. max. unit f xin clock input frequency - 12 / 27 - mhz xin duty clock input duty cycle 45 50 55 %
n3290 x datasheet nuvoton technology corp. 32 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.5.2 sdram interface mclk mcs_ mras_ mcas_ mwe_ ma mba t mclk t mdsu t mdh t mwl t mwh command out t moh t modly mdqs0 mdqs1 md[15:0] data output t mdqsh t mdqsl symbol parameter min. typ. max. unit t mclk mclk clock cycle time 6 - 12 ns t mwl mclk clock low time 0.45 - 0.55 t mclk t swh mclk clock high time 0.45 - 0.55 t mclk t modly command and address output delay time - - 2 ns t moh command and address output hold time 2 - - ns t mdqsh mdqs0/md qs1 high time 0.4 - 0.6 t mclk t mdqsl mdqs0/mdqs1 low time 0.4 - 0.6 t mclk t mdsu md to mdqs0/mdqs1 setup time 0.6 - - ns t mdh md to mdqs0/mdqs1 hold time 0.6 - - ns vref io reference voltage 0.49 - 0.51 vdd
n3290 x datasheet nuvoton technology corp. 33 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.5.3 sensor/video - in interface spclk shsync svsync sfield spdata[7:0] f spclk t sisu t sih t swl t swh symbol parameter min. typ. max. unit f spclk spclk clock frequency - - 50 mhz t swl spclk clock low t i me 10 - - ns t swh spclk clock high time 10 - - ns t sisu shsync, svsync, sfield, spdata[7:0] setup time 1.0 - - ns t sih shsync, svsyn c, sfield, spdata[7:0] hold time 1.0 - - ns
n3290 x datasheet nuvoton technology corp. 34 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.5.4 i2s interface i2s_bclk input mode i2s_ws i2s_dout output mode i2s_din f abclk t aoh t aisu t aih t awl t awh t aodly symbol parameter min. typ. max. unit f abclk i2s_bclk clock frequency - - 16 mhz t awl i2s_bclk clock low t i me 31.25 - - ns t awh i2s_bclk clock high time 31.2 5 - - ns t aisu i2s_din setup time 10 - - ns t aih i2s_din hold time 10 - - ns t aodly i2s_dout output delay time - - 0.5 ns t aoh i2s_dout output hold time 0.1 - - ns
n3290 x datasheet nuvoton technology corp. 35 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.5.5 lcd/display interface lpclk lhsync lvsync lvde lvdata[15:0] f lpclk t loh t lwl t lwh t lodly sync type lcd symbol parameter min. typ. max. unit f lpclk lpclk clock frequency - - 27 mhz t lwl lpclk clock low t i me 18.5 - - ns t lwh lpclk clock high time 18.5 - - ns t lodly lhsync, lvsync, lvde and lvdata output delay time - - 1.3 ns t loh lhsync, lvsync, lvde and lvdata output hold time 0. 67 - - ns
n3290 x datasheet nuvoton technology corp. 36 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 lpclk (cs_) lvsync (en) lhsync (wr_) t ldodly t ldoh t lwr lvdata[15:0] mpu type lcd lvde (rs) t las t lcss t lcsh t lah t len 80 mode: 68 mode: symbol parameter condition min. typ. max. unit t lcss cs_ to wr_ setup time 2 - - pclk t lcsh cs_ to wr_ hold time 1 - - pclk t las rs to wr_ setup time 1 - - pclk t lah rs to wr_ hold time 1 - - pclk t ldodl y lvdata output delay time - - 1 pclk t ldoh lvdata output hold time 1 - - pclk t lwr wr_ pulse width 80 mode 1 - - pclk t len en pulse width 68 mode 1 - - pclk note: pclk is the period of one apb bus clock.
n3290 x datasheet nuvoton technology corp. 37 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.5.6 spi interface spi0_clk input mode spi0_do output mode spi0_di f spclk t spoh t spisu t spih t spwl t spwh t spodly symbol parameter min. typ. max. unit f spclk spi0_clk clock frequency - - 25 mhz t spwl spi0_clk clock low t i me 20 - - ns t spwh spi0_clk clock high time 20 - - ns t spisu spi0_di setup time 10 - - ns t spih spi0_di hold time 10 - - ns t spodly sp i0_do output delay time - - 1 ns t spoh spi0_do output hold time 0.2 - - ns
n3290 x datasheet nuvoton technology corp. 38 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.5.7 nand interface ncs0_ ncs1_ nale ncle nre_ nwr_ t noh t nwl t nwh nd[7:0] ( write) nd[7:0] (read) t nisu t nih t nodly symbol parameter min. typ. max. unit t nwl write pulse low width 10 - - ns t nwh nwr_ high hold time 10 - - ns t nodly nd[7:0 ] output delay time - - 2.5 ns t noh nd[7:0] output hold time 10 - - ns t nisu nd[7:0] data in setup time 3.2 - - ns t nih nd[7:0] data in hold time 1 - - ns
n3290 x datasheet nuvoton technology corp. 39 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.5.8 sd card interface sdclk input mode sdcmd, sddat[3:0] output mode sdcmd, sddat[3:0] f sdclk t sdodly t sdoh t sdisu t sdih t sdwl t sdwh symbol parameter min. typ. max. unit clo ck sdclk f sdclk clock frequency in data transfer mode - - 24 mhz f sdclk clock frequency in identification mode 100 - 400 khz t sdwl clock low time 10 - - ns t sdwh clock high time 10 - - ns input sdcmd, sddat[3:0] (referenced to sdclk) t sdisu input set up time 6 - - ns t sdih input hold time 2 - - ns output sdcmd, sddat[3:0] (referenced to sdclk) t sdodly output delay time - - 14 ns t sdoh output hold time 2.5 - - ns
n3290 x datasheet nuvoton technology corp. 40 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 5.6 power - on sequence 5.7 thermal characteristics of lqfp - 128 package thermal perfo rmance of lqfp - 128 under forced convection
n3290 x datasheet nuvoton technology corp. 41 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 6. o r dering information par t no. package type description n3290 1u1 dn lqfp - 128 , mcp 1 stacked 1mbit x16 sdr mcp with lcd , cis and i2 s interface . N32903R1DN tqfp - 64, mcp stacked 4mbit x 16 ddr mcp with cis, sdhc and i2s interface n3290 3u1 dn lqfp - 128 , mcp stacked 4mbit x16 ddr mcp with lcd ,cis and i2 s interface . n3290 5u1 dn lqfp - 128 , mcp stacked 16mbit x16 ddr mcp with lcd , cis and i2s interface . n3290 5u2 dn lqf p - 128 , mcp stacked 16mbit x16 ddr mcp with lcd ,cis interf ace & tv output . 6.1 part number definition 6.2 difference between n32901u1dn, n32903u1dn, n32905u1dn and n32905u2dn mcped sdram type/capacity analog composite tv output i2s interface n32901u1dn sdr/2mbytes - v n32901u2dn sdr/2mbytes v - n32903u1dn ddr/8mb ytes - v n32905u1dn ddr/32mbytes - v n32905u2dn ddr/32mbytes v - 1 mcp stands for multi - chip package.
n3290 x datasheet nuvoton technology corp. 42 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 7. package outline 7.1 lqfp -128 (1 4 x1 4 x1.4mm body, 0.4mm pitch)
n3290 x datasheet nuvoton technology corp. 43 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 7.2 t qfp -64 (1 0 x1 0 x1. 0 mm body, 0. 5 mm pitch)
n3290 x datasheet nuvoton technology corp. 44 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1
n3290 x datasheet nuvoton technology corp. 45 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 unit: mm
n3290 x datasheet nuvoton technology corp. 46 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 7.3 l qfp -64 (1 0 x1 0 x1. 4 mm body, 0. 5 mm pitch) 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.004 0.10 3.5 3.5
n3290 x datasheet nuvoton technology corp. 47 release date: may. 2013 http:// www.nuvoton.com/ rev . a5.1 8. revision history version date page description a 0 jul . 25 , 201 2 all ? initial release . a 1 aug. 1, 2012 36 ? add stacked dram size into order information a2 aug. 30, 2012 all ? add n329 01u1dn information ? correct the n32905u2dn pin diagram a2.1 sept. 17, 2012 22 ? 1mx16 mvdd and mvddq are changed from 3.3v to 1.8v for consistence with n32905 and n32903 a3 oct. 15 , 2012 23,35 ? extend operation temperature range ? add parts feature difference table a3.1 oct. 26, 2012 35 ? add part number definition a3.2 nov. 8, 2012 6,7,8,9 ? add ccir still image and video recommanded resolutions. ? add lcd display for still image and video recommanded resolutions. ? modify one spi h/w engine to support two spi devic es by two chip selection signals when spi0 is in master mode. for lqfp128 package, only spi0 is active. ? add usb 1.1 host one h/w controller, three different pin locations information. a3.3 nov. 10, 2012 35 ? remove adobe flash feature from comparision tabl e. a 3.4 jan. 21, 2013 4, 5, 10, 23 ? update the ac characteristics. a 4.0 mar. 15, 2013 all ? add N32903R1DN a5.0 may. 1, 2013 all ? add n32901r1dn information. ? add n32901u2 dn information. a5.1 may. 3,2013 28 ? add sdram and ddr operation voltage spec importan t notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , ?insecure usage?. inse cure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage , customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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